The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple dielectric and conductor deposition processes followed by the masking and etching of the deposited layers. Some of these steps relate to metallization, which generally refers to the materials, methods and processes of wiring together or interconnecting the component parts of an integrated circuit located on or overlying the surface of the wafer. Typically, the “wiring” of an integrated circuit involves etching features, such as trenches and “vias,” in a planar dielectric (insulator) layer and filling the features with a conductive material, typically a metal.
In the past, aluminum was used extensively as a metallization material in semiconductor fabrication due to ease with which aluminum could be applied and patterned and due to the leakage and adhesion problems experienced with the use of gold. Other metallization materials have included such materials as Ni, Ta, Ti, W, Ag, Cu/Al, TaN, TiN, CoWP, NiP and CoP, alone or in various combinations.
Recently, techniques have been developed which utilize copper to form conductive contacts and interconnects because copper is less susceptible to electromigration and exhibits a lower resistivity than aluminum. Since copper does not readily form volatile or soluble compounds, the patterned etching of copper is difficult, and the copper conductive contacts and interconnects are therefore often formed using a damascene process. In accordance with the damascene process, the copper conductive contacts and interconnects are usually formed by creating a via within an insulating material. A barrier layer, which serves to prevent catastrophic contamination caused by copper diffusing through the interlayer dielectrics, may be deposited onto the surface of the insulating material and into the via. Because it is often difficult to form a copper metallization layer overlying the barrier layer, a seed layer of copper may be deposited onto the barrier layer. Then, a copper metallization layer is electrodeposited onto the seed layer to fill the via. The excess copper metallization layer, the copper seed layer, and the barrier layer overlying the insulating material then may be removed, for example by a process of chemical mechanical planarization or chemical mechanical polishing, each of which will hereafter be referred to as chemical mechanical planarization or CMP.
Barrier layers formed of tantalum (Ta) and tantalum nitride (TaN) currently are used to contain copper interconnects. However, it is difficult to deposit copper effectively onto thin barrier layers of Ta/TaN because the layers generally are too resistive, especially in high-aspect ratio features. In addition, it is difficult to fill high-aspect ratio features with copper due to the occurrence of copper voids. Poor sidewall coverage and large overhang surrounding the features cause the copper electrofill to close off and leave void defects in the features. As integrated circuits continue to scale to 90 nm nodes, 65 nm nodes, 45 nm nodes and smaller, it may become difficult to further decrease the dimensions of the Ta/TaN/Cu trilayer in higher-aspect ratio features. Preferable barrier layers should demonstrate good adhesion to both copper and interlayer dielectric materials, in addition to affording a conductive copper-plating platform that allows for the bottom-up copper electrofill of damascene features. Accordingly, as the aggressive scaling of semiconductor device dimensions continues, it is highly desirable to use a copper-plateable single-layer barrier layer for use in interconnects applications.
Barrier layers formed of ruthenium may present a desirable alternative to Ta/TaN barriers. Ruthenium is an air-stable transition metal with a high melting point and is nearly twice as thermally and electrically conductive as tantalum. In addition, ruthenium, like tantalum, generally shows negligible solid solubility with copper. However, ruthenium presents a particular challenge during CMP, as ruthenium is mechanically hard (Mohs hardness of approximately 6.5) and chemically resistant.
Accordingly, it is desirable to provide an improved method for the chemical mechanical planarization of ruthenium. In addition, it is desirable to provide improved chemical mechanical planarization compositions for removing ruthenium from a work piece. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.